ATMEGA162 PDF

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High-performance, Low-power AVR? A complete document is available on our Web site at www. Pin Configurations Figure 1. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology.

Min and Max values will be available after the device is characterized. By executing powerful instructions in a single clock cycle, the ATmega achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2. All the 32 registers are directly connected to the Arithmetic Logic Unit ALU , allowing two independent registers to be accessed in one single instruction executed in one clock cycle.

The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset.

In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega compatibility mode can be selected by programming the fuse MC. Also, the Extended Interrupt Vectors are removed.

However, the location of Fuse bits and the electrical characteristics differs between the two devices. The timed sequence for changing the Watchdog Time-out period is disabled. The location of these registers will not be affected by the ATmega compatibility fuse.

The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega as listed on page Port B PB The Port B output buffers have symmetrical drive characteristics with both high sink and source capability.

As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega as listed on page Port C PC The Port C output buffers have symmetrical drive characteristics with both high sink and source capability.

As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega as listed on page Port E PE The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated.

The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega as listed on page A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in Table 18 on page Shorter pulses are not guaranteed to generate a reset. Input to the Inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the Inverting Oscillator amplifier. For compatibility with future devices, reserved bits should be written to zero if accessed. Some of the Status Flags are cleared by writing a logical one to them. Rr Rd? Load Indirect and Pre-Dec. Store Indirect and Pre-Dec.

This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Also Halide free and fully Green. See Figure on page Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.

Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is 0. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.

The revision letter in this section refers to the revision of the ATmega device. There are no errata for this revision of ATmega Hence, captured data from the preceding devices in the boundary scan chain are lost and replaced by all-ones, and data to succeeding devices are replaced by all-ones during Update-DR.

If ATmega is the only device in the scan chain, the problem is not visible. Note that data to succeeding devices cannot be entered during this scan, but data to preceding devices can. Never read data from succeeding devices in the boundary scan chain or upload data to the succeeding devices while the Device ID Register is selected for the ATmega The referring revision in this section are referring to the document revision.

Added note on Figure 1 on page 2. Updated Table 18 on page 47 and Table 19 on page Updated description for the JTD bit on page Changes from Rev.

Corrected code examples on page Corrected OCn waveforms in Figure 52 on page Various minor Timer1 corrections. Updated Table 18 on page 47, Table 20 on page 49, Table 36 on page 76, Table 83 on page , Table on page , Table on page , and Table on page Updated Figure 29 on page 63, Figure 32 on page 67, and Figure 88 on page Added information for ATmegaU. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products.

Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice.

Atmel does not make any commitment to update the information contained herein. Atmel Corporation All rights reserved. Other terms and product names may be trademarks of others. Printed on recycled paper.

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